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september 2013 doc id 17242 rev 6 1/54 1 L99MD01 octal half-bridge driver with spi control for automotive application features 8 half bridges r on =typ. 0.9 (hs), 0.64 (ls) @t j =25c current limit of each output at min. 0.8 a intrinsic dc/dc step up converter driving an external mosfet pwm mode option for all half bridges for hold current internal pwm generation two current monitor outputs spi interface for data communication temperature warning all outputs overtemperature protected all outputs short circuit protected v cc supply voltage 3.0 to 5.3 v very low current consumption in standby mode typ. 5 a v s operating range compliant: 6 v ? 18 v applications stepper motor driver and / or dc intended to drive hvac flaps description the L99MD01 is an octal half-bridge driver for automotive applications. the device is intended to drive dc and/or stepper motors. using the boost converter it?s possible to drive 4 stepper motors simultaneously. without boost converter the system is able to run 3 stepper motors in sequential mode or 2 stepper motors simultaneously. the octal half bridge configuration allows also to drive 4 dc-motors simultaneously and 7 dc-motors sequentially. the integrated 24 bit standard serial peripheral interface (spi) controls all outputs and provides diagnostic information: normal operation, open- load in on-state, overcurrent, temperature warning and overtemperature. table 1. device summary package order codes tube tape and reel powersso-36 L99MD01xp L99MD01xptr powersso-36 *$3*&)7 www.st.com
contents L99MD01 2/54 doc id 17242 rev 6 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 power supply: v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 power supply: v sa , v sb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 smps switched mode power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.8 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.9 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . 9 2.10 v s , v s2 , v sa , v sb monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.11 open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.12 overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.13 cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.1 spi electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4.2 spi timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 functional description of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.2 serial data input (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
L99MD01 contents doc id 17242 rev 6 3/54 5.2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.2 command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.6 read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 spi control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 control status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 powersso-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1 ecopack ? package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2 powersso-36? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
list of tables L99MD01 4/54 doc id 17242 rev 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. v s , v s2 , v sa , v sb monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. current monitor dynamic characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 table 13. smps switched mode power supply gate driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 14. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 15. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 16. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 17. dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 18. command byte (8 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 20. operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 21. global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 22. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 23. ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 24. rom memory map (access with oc0 and oc1 set to ?1?) . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 25. control status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 26. control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 27. control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 28. control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 29. wobble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 30. frequency deviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 31. control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 32. ratio for curr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 33. ratio for curr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 34. control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 35. control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 36. status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 37. status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 38. status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 39. powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 40. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
L99MD01 list of figures doc id 17242 rev 6 5/54 list of figures figure 1. detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. pin connection (top view- not in scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. output turn-on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 5. smps timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. spi frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. indication of the global error flag on sdo when csn is low and sck is stable. . . . . . . . . 26 figure 10. driving 4 bipolar stepper motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11. driving 2 bipolar stepper motors simultaneously and 3 dc-motors sequentially . . . . . . . . 40 figure 12. driving 2 bipolar stepper motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 13. driving 1 bipolar stepper motor and 2 dc-motors simultaneously . . . . . . . . . . . . . . . . . . . 42 figure 14. driving 3 bipolar stepper motors sequentially . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15. driving 4 dc-motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16. driving 3 dc-motors simultaneously and 2 dc-motors sequentially . . . . . . . . . . . . . . . . . 45 figure 17. driving 7 dc-motors sequentially . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 18. driving simultaneously 4 unipolar winded stepper motors in bipolar mode . . . . . . . . . . . . 46 figure 19. cost saving impact using L99MD01 as stepper motor driver inside hvac systems . . . . . 47 figure 20. powersso-36 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 21. powersso-36 thermal impedance junction ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 22. powersso-36? package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 23. powersso-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 24. powersso-36 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
block diagram L99MD01 6/54 doc id 17242 rev 6 1 block diagram figure 1. detailed block diagram /2*,& *1' 9 v 63, 08; 9 v% 9 ff 9rowdjh0rqlwrulqj 3*1' 287 287 &855 &855 6&. '2 ', &61 (1 9 ff 9 ff 9 v$ 9 v% &xuuhqw 6hqvh 2yhufxuuhqw 2shqordg 287 287 287 287 9 v$ 3*1' 9 ff 9 ff &xuuhqw 6hqvh 2yhufxuuhqw 2shqordg &xuuhqw 0rqlwru 9 v 96wde 6036 &xuuhqw 6hqvh 2yhufxuuhqw 2shqordg &xuuhqw 6hqvh 2yhufxuuhqw 2shqordg 287 287 $*9
L99MD01 detailed description doc id 17242 rev 6 7/54 2 detailed description 2.1 power supply: v cc the supply voltage v cc (3.3 v / 5 v) supplies the whole device. in case of power-on (v cc increases from undervoltage to v por off = 2.75 v, typical) the circuit is initialized by an internally generated power-on-reset (por). if the voltage v cc decreases under the minimum threshold (v por on = 2.55 v, typical), the outputs are switched off in 3-state (high impedance). the status registers are cleared and the control registers are reset to their default. figure 2. power on reset 2.2 power supply: v sa , v sb each v sa and v sb supplies 4 half bridges independently. v sa ? out 1 to out 4 v sb ? out 5 to out 8 2.3 standby mode the standby mode of the L99MD01 is activated by en pin to low. the inputs and outputs are switched off. the status registers are cleared and the control registers are reset to their default values. in the standby mode the current consumption is typ. 5 a. 2.4 pwm mode the pwm mode is intended to generate a hold current for stepper motors. pwm frequency typ. 100 hz. duty cycle (spi 2bit): 15 %, 30 %, 45 % and 60 %. each half-bridge is independently addressable (spi 8bit). $*9 (1
detailed description L99MD01 8/54 doc id 17242 rev 6 2.5 smps switched mode power supply external mosfet spread spectrum technique: wobble oscillator, programmable by spi (1.95 k / 3.9 k / 7.8 k / 15.6 khz). frequency modulation programmable by spi (0 / 5 / 10 / 20%). v s2 level concept: microcontroller measuring pulse of smps frequency (dependent on internal oscillator frequency). due to the oscillator frequency of L99MD01 the c can calculate the on/off counts to program the smps frequency and duty cycle. microcontroller sending by spi smps 6-bit on counter value, microcontroller sending by spi smps 6-bit off counter value. basing on the on and off counter value the duty cycle and the smps frequency can be programmed. the v s2 voltage is strongly related to the duty cycle of smps. 2.6 current monitor the current monitor output sources a current image at the current monitor output which has a programmable ratio (1/250, 1/500, 1/750, 1/1000) of the instantaneous current of the selected half bridge (high-side or low-side). via spi it can be programmed which of the outputs are multiplexed to the current monitor output. the current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open or overload condition. for example this can be used to detect the motor state (starting, free-running, stalled). 2.7 inductive loads each half bridge is built by an internally connected high-side and a low-side power dmos transistor. due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs. 2.8 diagnostic functions all diagnostic functions (over/open-load, temperature warning and thermal shutdown, over/undervoltage) are internally filtered and the condition has to be valid for at least 32 s (open-load: typ. 2 ms, respectively) before the corresponding status bit in the status registers is set. the filters are used to improve the noise immunity of the device. open-load and temperature warning function are intended for information purpose and not changes the state of the output drivers. on contrary, the overload and thermal shutdown condition disables the corresponding driver (overload) or all drivers (thermal shutdown), respectively. the microcontroller has to clear the overcurrent status bit to reactivate the corresponding driver.
L99MD01 detailed description doc id 17242 rev 6 9/54 2.9 temperature warning and thermal shutdown if the junction temperature rises above t jtw on a temperature warning flag is set and is detectable via the spi. if the junction temperature increases above the second threshold t jsd on , the thermal shutdown bit is set and power dmos transistors of all output stages are switched off to protect the device. temperature warning flag and thermal shutdown bits are latched. in order to reactivate the output stages, the junction temperature must decrease below t jsd on and the thermal shutdown bit has to be cleared by the microcontroller. 2.10 v s , v s2 , v sa , v sb monitoring v s undervoltage: status bit is set. all outputs and smps are switched off. the microcontroller needs to clear the status bits to reactivate the drivers and smps. v s overvoltage: status bit is set. all outputs are switched off (default). the microcontroller needs to clear the status bits to reactivate the drivers can be deactivated via spi. v sa undervoltage: status bit is set. out 1 to out 8 are switched off. the microcontroller needs to clear the status bits to reactivate the drivers. v sb undervoltage: status bit is set. out 1 to out 8 are switched off. the microcontroller needs to clear the status bits to reactivate the drivers. v s2 undervoltage: status bit is set. only if spms is active. the microcontroller needs to clear the status bits to reactivate smps v s2 overvoltage: status bit is set. smps is switched off (default). the microcontroller needs to clear the status bits to reactivate smps. if the vs2 recovery bit is set, and the vs2 voltage falls below the threshold, the smps goes in active mode and the status bit is cleared. table 2. v s , v s2 , v sa , v sb monitoring ?typ smps out x v s undervoltage 5.7 v status + off status + off v s overvoltage 22.0 v x status + (off or mask) v sa undervoltage 5.7 v x status + off v sb undervoltage 5.7 v x status + off v s2 undervoltage v s + 1.5v status x v s2 overvoltage 35.0 v status + (off or (off+ recovery))
detailed description L99MD01 10/54 doc id 17242 rev 6 2.11 open-load detection the open-load detection monitors the load current in each activated output stage. if the load current is below the open-load detection threshold for at least 2 ms (t dol ) the corresponding open load bit is set in the status register. due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads. 2.12 overload detection in case of an overcurrent condition, a flag is set in the corresponding status register. if the overcurrent signal is valid for at least t isc = 32 s, the overcurrent flag is set and the corresponding switch is switched off to reduce the power dissipation and to protect the integrated circuit. the microcontroller has to clear the status bit to reactivate the corresponding driver. 2.13 cross-current protection the device is cross-current protected by an internal delay time. if one driver (ls or hs) is turned-off the activation of the other driver of the same half bridge are automatically delayed by the cross-current protection time. after the cross-current protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver starts to conduct. if wrong spi commands try to turn-on both driver (ls and hs) simultaneously, the high-side and the low-side are (or stay) deactivated (3-state).
L99MD01 pin definitions and functions doc id 17242 rev 6 11/54 3 pin definitions and functions table 3. pin description pin symbol function 1, 18, 19, 36 p gnd power ground: reference potential 9a gnd analog ground: reference potential 27 d gnd digital ground: reference potential 6, 10, 13 n.c. not connected exposed pad: reference potential connected to pgnd 2, 3, 16, 17, 20, 21, 34, 35 out 1 - 8 half bridge-output: the output is built by a high-side and a low-side switch, which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to v sx , low-side driver from pgnd to output). 29 v cc logic voltage supply 3.3 v / 5 v for this input a ceramic capacitor as close as possible to agnd is recommended 4, 5, 32, 33 v sa power supply voltage for out 1 to 4 (external reverse protection required): for this input a ceramic capacitor as close as possible to pgnd is recommended. important: for the capability of driving the full current at the outputs all pins of v sa must be externally connected! 14, 15, 22, 23 v sb power supply voltage for out 5 to 8 (external reverse protection required): for this input a ceramic capacitor as close as possible to pgnd is recommended. important: for the capability of driving the full current at the outputs all pins of v sa must be externally connected! 11 v s2mon v s2 monitoring 12 v s v s supply and monitoring 25 smps smps gate driver. for overcurrent and overvoltage protection a external resistor is recommended 7, 8 curr1 / 2 current monitor 1 / 2 31 en enable the L99MD01 28 di spi data in: the input requires cmos logic levels and receives serial data from the microcontroller. the data is a 24 bit control word and the most significant bit (msb) is transferred first. 26 do spi data out: the diagnosis data is available via the spi and this 3-state output. the output remains in 3-state, if the chip is not selected by the input csn (csn = high)
pin definitions and functions L99MD01 12/54 doc id 17242 rev 6 figure 3. pin connection (top view- not in scale) 24 csn spi csn chip select: this input is active low and requires cmos logic levels. the serial data transfer between the L99MD01 and micro controller is enabled by pulling the input csn to low level. 30 sck spi serial clock input: this input controls the internal shift register of the spi and requires cmos logic levels. table 3. pin description (continued) pin symbol function 3rzhu662 3 *1' 287 287 9 6$ 9 6$ 1& &855 &855 $ *1' 1& 9 6021 9 6 1& 9 6% 9 6% 287 287 3 *1' 3 *1' 287 287 9 6$ 9 6$ (1 6&. 9 && ', ' *1' '2 6036 &61 9 6% 9 6% 287 287 3 *1' $*9
L99MD01 electrical specifications doc id 17242 rev 6 13/54 4 electrical specifications 4.1 absolute maximum ratings note: all maximum ratings are absolute ratings. leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit! 4.2 esd protection table 4. absolute maximum ratings symbol parameter value unit v s dc supply voltage -0,3?28 v single pulse t max < 400 ms 40 v v s2 v sa v sb dc supply voltage -0,3?38 v single pulse t max < 400 ms 40 v v cc stabilized supply voltage, logic supply -0.3 to 5.5 v en di do sck csn digital input / output voltage -0.3 to v cc + 0.3 v curr1/2 current monitor output -0.3 to v cc + 0.3 out 1-8 output current capability 2 a smps smps is not overcurrent protected, external resistor can be used for protection and emc optimizations table 5. esd protection parameter value unit all pins 2 (1) 1. hbm according to eia/jesd22-a114-e. kv output pins: out1 ? 8, v s , v sa , v sb , v s2 , 4 (2) 2. hbm with all unzapped pins grounded. kv
electrical specifications L99MD01 14/54 doc id 17242 rev 6 4.3 thermal data 4.4 electrical characteristics v s = 6 to 18 v, v cc = 3.0 to 5.3 v, t j = -40 to 150 c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 6. operating junction temperature symbol parameter value unit t j operating junction temperature -40 to 150 c table 7. temperature warning and thermal shutdown symbol parameter min. typ. max. unit t jtw on temperature warning threshold junction temperature t j increasing - - 150 c t jsd on thermal shutdown threshold junction temperature t j increasing - - 170 c table 8. supply symbol parameter test condition min. typ. max. unit v sa / v sb operating supply voltage range 638v i s v sa / v sb dc supply current v sx = 13 v, v cc = 5.0 v en = high outputs floating 0.5 2 ma i vs v s supply current v s = 13 v, v cc = 5 v en = high smps output off 1.5 4 ma v s = 13 v, v cc = 5 v en = high smps load = 2 nf, 200 khz, duty 50 % 4.2 7 ma i vs2 v s2 dc current v s2 =26 v, v cc = 5.0 v en = high 300 600 a i vsx v sx (v s , v sa , v sb , v s2 ) quiescent supply current v sx = 13 v, v cc = 5 v en = low t j = -40, 25 c outputs floating 310a t j = 130 c; tbv 6 20 a v cc operating supply voltage range 3,0 5,3 v
L99MD01 electrical specifications doc id 17242 rev 6 15/54 i cc v cc dc supply current v sx = 13 v, v cc = 5.0 v en = high 13ma v cc quiescent supply current v s = 13 v, v cc = 5.0 v csn = v cc en = low outputs floating 520a table 8. supply (continued) symbol parameter test condition min. typ. max. unit table 9. overvoltage and undervoltage detection symbol parameter test condition min. typ. max. unit v por off power-on-reset threshold v cc increasing 3.0 v v por on power-on-reset threshold v cc decreasing 2.3 v v por hyst power-on-reset hysteresis v por off - v por on 0.2 v v suv off v s uv-threshold voltage v s increasing 6.0 6.7 v v suv on v s uv-threshold voltage v s decreasing 5.4 6 v v suv hyst v s uv-hysteresis v suv off - v suv on 0.35 0.5 v v sauv off v sa uv-threshold voltage v sa increasing 5.95 6.7 v v sauv on v sa uv-threshold voltage v sa decreasing 5.4 6 v v sauv hyst v sa uv-hysteresis v sauv off - v sauv on 0.35 0.5 v v sbuv off v sb uv-threshold voltage v sb increasing 5.95 6.7 v v sbuv on v sb uv-threshold voltage v sb decreasing 5.4 6 v v sbuv hyst v sb uv-hysteresis v sbuv off - v sbuv on 0.35 0.5 v v sov on v s ov-threshold voltage v s increasing 24 v v sov off v s ov-threshold voltage v s decreasing 18 v v sov hyst v s ov-hysteresis v sov on - v sov off 0.75 1 v v s2uv off v s2 uv-threshold voltage v s2 increasing v s +5 v v s2uv on v s2 uv-threshold voltage v s2 decreasing v s +1 v v s2uv hyst v s2 uv-hysteresis v s2uv off - v s2uv on 0.55 0.8 1.15 v v s2ov on v s2 ov-threshold voltage v s increasing 38 v v s2ov off v s2 ov-threshold voltage v s decreasing 32 v v s2ov hyst v s2 ov-hysteresis v s2ov on - v s2ov off 0.75 1 v
electrical specifications L99MD01 16/54 doc id 17242 rev 6 table 10. switches symbol parameter test condition min. typ. max. unit r on hs 1-8 on resistance v sa / v sb to out 1-8 t j = 25 c, i out1-8 = -0.25 a 900 1200 m t j = 125 c, i out1-8 = -0.25 a 1300 1800 m r onlshc 1-8 on resistance out 1-8 to gnd in hc mode t j = 25 c, hc=1 i out1-8 = 0.25 a 700 1000 m t j = 125 c, hc=1 i out1-8 = 0.25 a 1000 1500 m r onlslc 1-8 on resistance out 1-8 to gnd in lc mode t j = 25 c, hc=0 i out1-8 = 0.125 a 1200 1800 m t j = 125 c, hc=0 i out1-8 = 0.125 a 2000 2800 m i schs1-8 hs overcurrent protection v s = 13.5 v 0.8 1.4 a i sclshc1-8 ls overcurrent protection in hc mode v s = 13.5 v, hc = 1 0.8 1.4 a i sclslc1-8 ls overcurrent protection in lc mode v s = 13.5 v, hc = 0 0.4 0.7 a t d on1-8 h output delay time, hs switch on v s = 13.5 v, r load = 52 10 25 80 s t d off1-8 h output delay time, hs switch off v s = 13.5 v, r load = 52 50 100 300 s t d on1-8 l output delay time, ls switch on v s = 13.5 v, r load = 52 51580s t d off1-8 l output delay time, ls switch off v s = 13.5 v, r load = 52 50 100 300 s t d lh /t d hl cross current protection time 20 200 400 s i qlh switched-off output current hs out 1-8 v out1-8 = 0 v -2 a i qll switched-off output current ls out 1-8 v out1-8 = v s 2a i oldhs1-8 open-load detection current hs out 1-8 t j =-40c 8 30 60 ma t j = 25 c to 125 c 10 30 60 ma i oldlshc1-8 open-load detection current ls out 1-8 in hc mode hc bit set to 1; t j = -40 c 4.5 30 65 ma hc bit set to 1; t j = 25 c to 125 c 83060ma i oldlslc1-8 open-load detection current ls out 1-8 in lc mode hc bit set to 0; t j = -40 c 1.8 15 35 ma hc bit set to 0; t j = 25 c to 125 c 41530ma t dol minimum duration of open-load condition to set the status bit 500 2000 3000 s
L99MD01 electrical specifications doc id 17242 rev 6 17/54 figure 4. output turn-on/off delays and slew rates t isc minimum duration of overcurrent condition to switch off the driver 10 32 100 s dv out1-8 /dt slew rate of out 1-8 v s = 13.5 v, r load = 52 0.10.250.5v/s table 10. switches (continued) symbol parameter test condition min. typ. max. unit *1' *1' / rz6lgh + ljk6lgh 9 287; 9 287; w g21[/+ g9rxw[gw *1' /rz6lgh +ljk6lgh 9 287; 9 287; w g2))[/+ g9rxw[gw *1' $*9 table 11. current monitor output symbol parameter test condition min. typ. max. unit v curr1/2 functional voltage range v cc = 5 v 0 v cc -1 v i currhsls250 hs/ls current monitor output ratio: i curr1/2 / i out 1- 8 0v v curr1/2 v cc -1v, v cc = 5 v; prog. via spi, i max =800ma, hc=1 1/250 - i currhsls500 hs/ls current monitor output ratio: i curr1/2 / i out 1- 8 0v v curr1/2 v cc -1v, v cc = 5 v; prog. via spi, i max =800ma, hc=1 1/500 - i currhsls750 hs/ls current monitor output ratio: i curr1/2 / i out 1- 8 0v v curr1/2 v cc -1v, v cc = 5 v; prog. via spi, i max =800ma, hc=1 1/750 - i currhsls1000 hs/ls current monitor output ratio: i curr1/2 / i out 1- 8 0v v curr1/2 v cc -1v, v cc = 5 v; prog. via spi, i max =800ma, hc=1 1/1000 - i currlslc125 ls current monitor output ratio in lc mode: i curr1/2 / i out 1-8 0v v curr1/2 v cc -1v, v cc = 5 v; prog. via spi, hc = 0; i max = 400 ma 1/125 -
electrical specifications L99MD01 18/54 doc id 17242 rev 6 i currlslc250 ls current monitor output ratio in lc mode: i currlslc1/2 / i out 1-8 0v v curr1/2 v cc -1v, v cc = 5 v; prog. via spi, hc = 0; i max = 400 ma 1/250 - i currlslc375 ls current monitor output ratio in lc mode: i curr1/2 / i out 1-8 0v v curr1/2 v cc -1v, v cc = 5 v; prog. via spi, hc = 0; i max = 400 ma 1/375 - i currlslc500 ls current monitor output ratio in lc mode: i curr1/2 / i out 1-8 0v v curr1/2 v cc -1v, v cc = 5 v; prog. via spi, hc = 0; i max = 400 ma 1/500 - i currhs1/2 acc hs current monitor accuracy 0v v curr1/2 v cc -1v, v cc =5v; i out 1-8 max =0.8a (fs = full scale= 800 ma*current ratio); t j =- 40 c 4% + 1%fs 10% + 3%fs - 0v v curr1/2 v cc -1v, v cc =5v; i out 1-8 max =0.8a; (fs = full scale= 800 ma*current ratio); t j = 25 c to 125 c 4% + 1%fs 8% + 2%fs i currlshc1/2 acc ls current monitor accuracy in hc mode 0v v curr1/2 v cc -1v, v cc =5v; 0.4 a i out1-8 0.8 a (fs = full scale= 800 ma*current ratio) 4% + 1%fs 10% + 3%fs - i currlslc1/2 acc ls current monitor accuracy in lc mode 0v v curr1/2 v cc -1v, v cc =5v; i out 1-8 max = 0.4 a (fs = full scale= 800 ma*current ratio) 4% + 1%fs 10% + 3%fs - table 11. current monitor output (continued) symbol parameter test condition min. typ. max. unit table 12. current monitor dynamic characteristics symbol parameter test condition min. typ. max. unit t d-cm output to current monitor delay time i out from 100 ma to 200 ma; t d-cm measured from 50 % i out to 50 % icm ?2?s table 13. smps switched mode power supply gate driver output symbol parameter test condition min. typ. max. unit v smpshi smps output voltage high v s = 8 v, i smps = -10 ma 4.5 5.5 6.5 v v smpl smps output voltage low v s = 8 v, i smps = 10 ma 100 mv t smpsh output rise time v s = 13.5 v, cout = 2 nf 110 160 ns t smpsl output fall time v s = 13.5 v, cout = 2 nf 110 160 ns
L99MD01 electrical specifications doc id 17242 rev 6 19/54 figure 5. smps timings 4.4.1 spi electrical characteristics v s = 6 to 18 v, v cc = 3.0 to 5.3 v, t j = -40 to 150 c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. t donsmps output delay time, switch to high v s = 13.5 v, cout = 2 nf 110 160 ns t doffsmps output delay time, switch to low v s = 13.5 v, cout = 2 nf 30 100 ns t don-offsmps output delay time difference on/off v s = 13.5 v, cout = 2 nf 80 120 ns r smps pull down resistor, smps 23 50 100 k table 13. smps switched mode power supply gate driver output symbol parameter test condition min. typ. max. unit table 14. oscillator symbol parameter test condition min. typ. max. unit f clk internal clock frequency 2.8 4 5.2 mhz 7 g216036 w 6036+ 9 6036 7 g2))6036 *1' w 6036/ $*9 table 15. dc characteristics symbol parameter test condition min. typ. max. unit sdi, sck, csn, en v il input low voltage 0.3v cc v v ih input high voltage 0.7v cc v i csn in pull up current at input csn v csn = 1.5 v; v cc = 5 v 8 20 40 a
electrical specifications L99MD01 20/54 doc id 17242 rev 6 i sck in pull down current at input sck v sck = 1.5 v; v cc = 5 v 10 25 50 a i di in pull down current at input di v di = 1.5 v; v cc = 5 v 10 25 50 a r en in pull down resistor at input en v en = 1.5 v; v cc = 5 v 25 50 115 k sdo v ol output low voltage i out = 2 ma 0.2 0.4 v v oh output high voltage i out = +2 ma v cc - 0.4 v cc - 0.2 v i dolk 3-state leakage current v csn = v cc , 0v < v cc -10 10 a table 16. ac characteristics symbol parameter test condition min. typ. max. unit sdo, sdi, sck, csn, en c out (1) 1. guaranteed by design output capacitance (sdo) v out = 0 v to 5 v ? ? 10 pf c in (1) input capacitance (sdi) v in = 0 v to 5 v ? ? 10 pf input capacitance (other pins) v in = 0 v to 5 v ? ? 10 pf table 17. dynamic characteristics (1) symbol parameter test condition min. typ. max. unit t en en high setup time 100 s t scsn csn setup time before sck rising 400 ns t hcsn csn high time 2 s t csnqv csn falling until sdo valid c out = 100 pf 100 ns t csnqt csn rising until sdo 3-state c out = 100 pf 150 ns t ssck sck setup time before csn rising 50 ns t ssdi sdi setup time before sck rising 40 ns t hsck sck high time 200 ns t lsck sck low time 200 ns t sckqv sck falling until sdo valid c out = 100 pf 150 ns table 15. dc characteristics (continued) symbol parameter test condition min. typ. max. unit
L99MD01 electrical specifications doc id 17242 rev 6 21/54 4.4.2 spi timing parameter definition figure 6. spi timing t qlqh output rise time c out = 100 pf, 20 % - 80 % x v cc 110 ns t qhql output fall time c out = 100 pf, 80 % - 20 % x v cc 110 ns f spi spi frequency 1 mhz 1. see section 4.4.2: spi timing parameter definition . table 17. dynamic characteristics (1) symbol parameter test condition min. typ. max. unit w &6149 &61idoolqjxqwlo6'2ydolg w 6&.49 6&.ulvlqjxqwlo6'2ydolg w 6&61 &61vhwxswlphehiruh6&.ulvlqj w 66', 6',vhwxswlphehiruh6&.ulvlqj w +6&. plqlpxp6&.kljkwlph w /6&. plqlpxp6&.orzwlph w +&61 plqlpxp&61kljkwlph w &6147 &61ulvlqjxqwlo6'2wulvwdwh w 66&. 6&.vhwxswlphehiruh1&6ulvlqj &6 1 6' 2 'dwdrxw w &6147 w 6&.49 6& . 'dwdrxw w +6&. w /6&. w 6&61 w +&61 'dwdlq 'dwdlq w 66', 6' , w &6149 w 66&. $*9
functional description of the spi L99MD01 22/54 doc id 17242 rev 6 5 functional description of the spi 5.1 signal description 5.1.1 serial clock (sck) this input signal provides the timing of the serial interface. data present at serial data input (sdi) is latched on the rising edge of serial clock (sck). data on serial data out (sdo) is shifted out at the falling edge of serial clock (see 2 h figure 7 ). the spi can be driven by a microcontroller with its spi peripherals running in following mode: cpol=0 and cpha=0 (see 3 h figure 7 ). 5.1.2 serial data input (sdi) this input is used to transfer data serially into the device. it receives the data to be written. values are latched on the rising edge of serial clock (sck). serial data output (sdo) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (sck). sdo also reflects the status of the (bit 7 of the ) while csn is low and no clock signal is present. chip select not (csn) when this input signal is high, the device is deselected and serial data output (sdo) is high impedance (3-state). driving this input low enables the communication. the communication must start and stop on a low level of serial clock (sck). figure 7. clock polarity and clock phase &32/&3+$ &61 6&. 6', 6'2 06% /6% 06% /6% +, +, *$3*&)7
L99MD01 functional description of the spi doc id 17242 rev 6 23/54 figure 8. spi frame structure &61 6'2 6', 06% 06% /6% /6% :ulwh 2shudwlrq &61 6'2 6', *oredo6wdwxv %\wh elw 06% 06% /6% /6% 'dwd 5hdg 2shudwlrq 06% /6% 06% /6% elw &rppdqg %\wh elw *oredo6wdwxv %\wh elw &rppdqg %\wh elw 'rq?wfduh elw 'dwd suhylrxvfrqwhqwriuhjlvwhu 'dwd elw *$3*&)7
functional description of the spi L99MD01 24/54 doc id 17242 rev 6 5.2 spi communication flow 5.2.1 general description the proposed spi communication is based on a standard spi interface structure using csn (chip select not), sdi (serial data in), sdo (serial data out/error) and sck (serial clock) signal lines. maximum spi frequency is 1 mhz. at the beginning of each communication the master reads the register (rom address 3eh) of the slave device. this 8-bit register indicates the spi frame length (24-bit for the L99MD01) and the availability of additional features. each communication frame consists of an instruction byte which is followed by 2 data bytes (see 4 h figure 8 ). the data returned on sdo within the same frame always starts with the register. it provides general status information about the device. it is followed by 2bytes (i. e. ?in-frame-response?, figure 8 ). for write cycles the register is followed by the previous content of the addressed register. for read cycles the register is followed by the content of the addressed register. 5.2.2 command byte each communication frame starts with a command byte. it consists of an operating code which specifies the type of operation (, , , ) and a 6 bit address. table 18. command byte (8 bit) operating code address bit 2322212019181716 name oc1 oc0 a5 a4 a3 a2 a1 a0 table 19. data byte data byte 1 data byte 0 bit1514131211109876543210 name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 20. operating code definition oc1 oc0 meaning 0 0 0 1 1 0 1 1
L99MD01 functional description of the spi doc id 17242 rev 6 25/54 the and operations allow access to the ram of the device, i. e. write to control registers or read status information. a operation addressed to a device specific status register reads back and subsequently clear this status register. a operation with address 3fh clears all status registers at a time and reads back the register. a operation addressed to an unused ram address register is identical to a operation (in case of unused ram address, the second byte is equal to 00h). allows access to the rom area which contains device related information such as the product family, product name, silicon version and register width. the is generated by an or-combination of all failure events of the device (i.e. bit 0 to bit 6 of the < global status byte> . table 21. global status byte bit description polarity comment 0 software reset or under/overvoltage active high depends on bit 5 of < global status byte> : bit 5 bit 0 0 set if software reset (sdi stuck at 1 or 0) 1 logical or of the under- / overvoltage status bits 1 overcurrent detected active high set by any overcurrent event 2 open-load detected active high set by any open-load event 3 temp warning active high 4 thermal shutdown / chip overload active high 5 not (chip reset or communication error) active low activated by all internal reset events that change device state or configuration registers (e. g. software reset, v cc under-voltage, etc.). the bit is set after a valid communication with any register. this bit is initially ?0? and is set to ?1? by a valid spi communication 6 communication error active high bit is set if the number of clock cycles during csn = low does not match with the specified frame width or if an invalid bus condition is detected (sdi stuck at 1 or 0). 7 global error flag active high logic or combination of all failures in the .
functional description of the spi L99MD01 26/54 doc id 17242 rev 6 figure 9. indication of the global error flag on sdo when csn is low and sck is stable. the bit 0 of the < global status byte> is a combination of an under/overvoltage warning and a software warning: if the bit 5 is one (this is the standard after a correct spi communication), bit 0 is the logical or of all under- and overvoltage status bits. on the other hand, if there has been an spi communication error or a chip reset (bit 5 is zero), then bit 0 gives a better indication about the spi error: an sdi stuck-at error leads to a software reset and sets bit 0, while a clock pulse error only sets the communication error bit, clears bit 5 and clears also bit 0. this leads to the following table of possible states (assuming there is no under/overvoltage, overcurrent, openload or thermal error): writing to the selected data input register is only enabled if exactly one frame length is transmitted within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame, the complete frame is ignored and a spi frame error is signaled in the global status register. this safety function is implemented to avoid an unwanted activation of output stages by a wrong communication frame. &61 6&. 6', 6'2 &61kljkwrorzdqg6&.vwd\v6wdeohkljkruorz*oredo(uur u)odjelwri?*oredo6wdwxv%\wh3lv wudqvihuhgwr6'2 wlph wlph wlph wlph ',gdwdlvqrwdffhswhg 6'2*oredo(uuru)odj%lwri?*oredo6wdwxv%\wh3zloovwd \dvorqj&61lvorz *() *$3*&)7 table 22. reset state description global status en = 0 (power on reset) all registers reset outputs switched off (3-state) 1000 0000 clock cycles != 24 ignore frame no reset 1100 0000 sdi always 0 software reset outputs switched off 1100 0001 sdi always 1 software reset outputs switched off 1100 0001
L99MD01 functional description of the spi doc id 17242 rev 6 27/54 for read operations, the bit in the is set, but the register to be read is still transferred to the sdo pin. if the number of clock cycles is smaller than the frame width, the data at sdo are truncated. if the number of clock cycles is larger than the frame width, the data at sdo are filled with ?0? bits. due to this safety functionality a daisy chaining of spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ics is recommended. note: as the frame width is 24 bits, an initial read of using a 16 bits communication sets the of the . a subsequent correct length transaction is necessary to correct this bit. 5.3 write operation oc0, oc1: operating code (00 for ?write? mode) the write operation starts with a command byte followed by 2 data bytes. for write cycles the register is followed by the previous content of the addressed register. the ram memory area consists of 16 bit registers. all unused ram addresses are read as ?0?. failures are indicated by activating the corresponding bit of the register. note: ram address 00h is unused. an attempt to access this address is recognized as a communication line error (?data-in stuck to gnd?) and all internal registers are cleared (software reset). 5.4 read operation oc0, oc1: operating code (01 for ?read? mode) the read operation starts with a command byte followed by 2 data bytes. the content of the data bytes is ?don?t care?. the content of the addressed register is shifted out at sdo within the same frame (?in-frame response?). the returned data byte represents the content of the register to be read. failures are indicated by activating the corresponding bit of the register. 5.5 read and clear status operation oc0, oc1: operating code (10 for ?read and clear status? mode) the ?read and clear status? operation starts with a command byte followed by 2 data bytes. the content of the data bytes is ?don?t care?. the content of the addressed status register is transferred to sdo within the same frame (?in-frame response?) and is subsequently cleared. a ?read and clear status? operation with address 3fh clears all status registers simultaneously.
functional description of the spi L99MD01 28/54 doc id 17242 rev 6 a operation addressed to an unused ram address is identical to a operation (in case of unused ram address, the second byte is equal to 00h). the returned data byte represents the content of the register to be read. failures are indicated by activating the corresponding bit of the register. 5.6 read device information oc0, oc1: operating code (11 for ?read device information mode). the device information is stored at the rom in the rom memory area, the first 8 bits are used. all unused rom addresses are read as ?0?. note: rom address 3fh is unused. an attempt to access this address is recognized as a communication line error (?data-in stuck to v cc ?) all internal registers are cleared (software reset).
L99MD01 spi control and status register doc id 17242 rev 6 29/54 6 spi control and status register table 23. ram memory map address name access content 01h control register 1 read/write output switch on/off 02h control register 2 read/write smps driver configuration 03h control register 3 read/write low-side high current mode v s configuration smps configuration 04h control register 4 read/write current multiplexer 05h control register 5 read/write pwm 06h control register 6 read/write open-load 10h status register 0 read only overcurrent 11h status register 1 read only open-load 12h status register 2 read only tsd over/undervoltage table 24. rom memory map (access with oc0 and oc1 set to ?1?) address name access content 00h id header read only 43h (device class assp, 2 additional information bytes) 01h version read only 00h (engineering samples) (st-spi) 02h produccode1 read only 3eh (62 st_spi) 03h produccode2 read only 4eh (n st_spi) 3dh fuses read only fuse data 9 - 0 3eh spi-frame id read only 02h spi-frame-id register (24 bit st_spi)
spi control and status register L99MD01 30/54 doc id 17242 rev 6 6.1 control status register default reset value is 0, all unused bits read 0, unused bits have to be set to 0 table 25. control status register address access data byte 1 data byte 0 1514131211109876543210 01h r/w hs8 ls8 hs7 ls7 hs6 ls6 hs5 ls5 hs4 ls4 hs3 ls3 hs2 ls2 hs1 ls1 output switch on/off 1514131211109876543210 02h r/w 0 0 on on on on on on 0 0 off off off off off off on/off cycles counter for smps driver (off must be > 3dec.) 1514131211109876543210 03h r/w hc8 hc7 hc6 hc5 hc4 hc3 hc2 hc1 0 v s ov warn/ shutdown v s2 reco. wob wob freq dev. freq dev. rnd/ lin low-side high current (reset value = 1) smps configuration 1514131211109876543210 04h r/w outx to curr2 outx to curr2 outx to curr2 outx to curr2 outx to curr1 outx to curr1 outx to curr1 outx to curr1 0000 2k- fact 2k-fact 1k-fact 1k-fact current multiplexer 1514131211109876543210 05hr/w000000pwm duty out8 out7 out6 out5 out4 out3 out2 out1 pwm 1514131211109876543210 06hr/w00000000 disable ol8 disable ol7 disable ol6 disable ol5 disable ol4 disable ol3 disable ol2 disable ol1 open-load 1514131211109876543210 10h r hs8 ls8 hs7 ls7 hs6 ls6 hs5 ls5 hs4 ls4 hs3 ls3 hs2 ls2 hs1 ls1 status overcurrent
L99MD01 spi control and status register doc id 17242 rev 6 31/54 1514131211109876543210 11hr 00000000 out8 out7 out6 out5 out4 out3 out2 out1 status open-load 1514131211109876543210 12hr 00000000 tsd tsd warn v s2 uv v s2 ov v s uv v s ov v sb uv v sa uv status tsd; over/ undervoltage table 25. control status register (continued) address access data byte 1 data byte 0 table 26. control register 1 bit control register 1 (read/write); address 01h name comment 15 out8 ? hs on/off if a bit is set, the selected output driver is switched on. if the corresponding pwm enable bit is set the driver is pwmed. if the bits of hs- and ls-driver of the same half bridge are set, the hs- and the ls-driver is deactivated. 14 out8 ? ls on/off 13 out7 ? hs on/off 12 out7 ? ls on/off 11 out6 ? hs on/off 10 out6 ? ls on/off 9 out5 ? hs on/off 8 out5 ? ls on/off 7 out4 ? hs on/off 6 out4 ? ls on/off 5 out3 ? hs on/off 4 out3 ? ls on/off 3 out2 ? hs on/off 2 out2 ? ls on/off 1 out1 ? hs on/off 0 out1 ? ls on/off
spi control and status register L99MD01 32/54 doc id 17242 rev 6 table 27. control register 2 bit control register 2 (read/write); address 02h name comment smps frequency and duty cycle. 15 - 14 - 13 smps on cycles bit 5 number of on cycles for smps driver, binary coded. cycles are based on the internal oscillator if all bits are set to ?1? the smps output is high for 63 clock cycles. 12 smps on cycles bit 4 11 smps on cycles bit 3 10 smps on cycles bit 2 9 smps on cycles bit 1 8 smps on cycles bit 0 7- 6- 5 smps off cycles bit 5 number of off cycles for smps driver, binary coded. cycles are based on the internal oscillator. if off is set to values 3 the smps driver is switched off. if all bits are set to ?1? the smps output is low for 63 clock cycles. 4 smps off cycles bit 4 3 smps off cycles bit 3 2 smps off cycles bit 2 1 smps off cycles bit 1 0 smps off cycles bit 0 table 28. control register 3 bit control register 3 (read/write); address 03h name comment 15 high current ls 8 high current mode of low-side switch ?0?: the selected low-side switch is in low current mode. the overcurrent and open-load thresholds are reduced by ?. the selected current monitor ratio is doubled. ?1? (default setting) the selected low-side switch is in high current mode 14 high current ls 7 13 high current ls 6 12 high current ls 5 11 high current ls 4 10 high current ls 3 9 high current ls 2 8 high current ls 1 7- 6v s ov shutdown/warn in case of v s overvoltage ?0?: all outputs are switched off + status bit set ?1?: only status bit is set
L99MD01 spi control and status register doc id 17242 rev 6 33/54 5v s2 recovery v s2 recovery mode: ?0?: no recovery after v s2 overvoltage ?1?: if the v s2 voltage falls below the threshold after a v s2 overvoltage condition, the smps goes again in active mode and the status bit is cleared smps configuration 4 wobble bit 1 wobble defines the modulation frequency deviation of the internal oscillator, definition see table 29 . 3 wobble bit 0 2 frequency deviation bit 1 frequency deviation of the internal oscillator, definition see table 30 1 frequency deviation bit 0 0 rnd/lin random/linear mode: ?0?: the oscillator is changed in linear mode like a triangle. ?1?: the oscillator frequency is distributed randomly. table 28. control register 3 (continued) bit control register 3 (read/write); address 03h name comment table 29. wobble bit 4 bit 3 wobble 0 0 1.95 khz 0 1 3.9 khz 1 0 7.8 khz 1 1 15.6 khz table 30. frequency deviation bit 2 bit 1 frequency deviation 00 0% 01 5% 10 10% 11 20%
spi control and status register L99MD01 34/54 doc id 17242 rev 6 table 31. control register 4 bit control register 4 (read/write); address 04h name comment 15 outx to curr2 bit 2 bit setting 111 110 101 100 011 010 001 000 14 outx to curr2 bit 1 to curr2 out8 out7 out6 out5 out4 out3 out2 out1 13 outx to curr2 bit 0 12 enable curr2 enable the current monitor output 2 11 outx to curr1 bit 2 bit setting 111 110 101 100 011 010 001 000 10 outx to curr1 bit 1 to curr1 out8 out7 out6 out5 out4 out3 out2 out1 9 outx to curr1 bit 0 8 enable curr1 enable the current monitor output 1 7- 6- 5- 4- 3 curr2 k-factor current monitor ratio i outx /i curr if the high current bit (register 03h) is set to 0 the ratio for the low-side is the double of the programmed one. 2 curr2 k-factor 1 curr1 k-factor 0 curr1 k-factor table 32. ratio for curr2 bit3 bit2 ratio for curr2 0 0 1/1000 01 1/750 10 1/500 11 1/250 table 33. ratio for curr1 bit1 bit0 ratio for curr1 0 0 1/1000 01 1/750 10 1/500 11 1/250
L99MD01 spi control and status register doc id 17242 rev 6 35/54 table 34. control register 5 bit control register 5 (read/write); address 05h name comment 15 - 14 - 13 - 12 - bit 9 bit 8 pwm duty cycle 11 - 0 0 15 % 10 - 0 1 30 % 9 pwm duty bit 1 1 0 45 % 8 pwm duty bit 0 1 1 60 % 7 pwm to out 8 pwm enable ?0?: pwm disabled for this output ?1?: if the corresponding enable bit is set and the pwm bit is set to ?1? the programmed output is pwm?ed with typical 100 hz 6 pwm to out 7 5 pwm to out 6 4 pwm to out 5 3 pwm to out 4 2 pwm to out 3 1 pwm to out 2 0 pwm to out 1
spi control and status register L99MD01 36/54 doc id 17242 rev 6 table 35. control register 6 bit control register 6 (read/write); address 06h name comment 15 - 14 - 13 - 12 - 11 - 10 - 9- 8- 7disable ol out8 disable the open-load measurement ?0?: open-load is signaled via the corresponding bit in status register 2 and the global error byte ?1?: in case of an open-load, no register changes. also the global error register not changes. 6disable ol out7 5disable ol out6 4disable ol out5 3disable ol out4 2disable ol out3 1disable ol out2 0disable ol out1
L99MD01 spi control and status register doc id 17242 rev 6 37/54 table 36. status register 0 bit status register 0 (read only); address 10h name comment 15 hs8 overcurrent error detected, driver is deactivated 14 ls8 13 hs7 12 ls7 11 hs6 10 ls6 9hs5 8ls5 7hs4 6ls4 5hs3 4ls3 3hs2 2ls2 1hs1 0ls1 table 37. status register 1 bit status register 1 (read only); address 11h name comment 15-8 - - 7 open-load out8 open-load detected, information only no changes if the corresponding disable ol bit (control register 6) is set 6 open-load out7 5 open-load out6 4 open-load out5 3 open-load out4 2 open-load out3 1 open-load out2 0 open-load out1
spi control and status register L99MD01 38/54 doc id 17242 rev 6 table 38. status register 2 bit status register 2 (read only); address 12h name comment 15-8 - - 7 tsd overtemperature detected: all the drivers are switched off 6 tsd warning overtemperature warning level detected, information only 5v s2 uv v s2 undervoltage 4v s2 ov v s2 overvoltage 3v s uv v s undervoltage 2v s ov v s overvoltage 1v sb uv v sb undervoltage 0v sa uv v sa undervoltage
L99MD01 application examples doc id 17242 rev 6 39/54 7 application examples figure 10. driving 4 bipolar stepper motors simultaneously $*9
application examples L99MD01 40/54 doc id 17242 rev 6 figure 11. driving 2 bipolar stepper motors simultaneously and 3 dc-motors sequentially $*9
L99MD01 application examples doc id 17242 rev 6 41/54 figure 12. driving 2 bipolar stepper motors simultaneously $*9
application examples L99MD01 42/54 doc id 17242 rev 6 figure 13. driving 1 bipolar stepper motor and 2 dc-motors simultaneously $*9
L99MD01 application examples doc id 17242 rev 6 43/54 figure 14. driving 3 bipolar stepper motors sequentially $*9
application examples L99MD01 44/54 doc id 17242 rev 6 figure 15. driving 4 dc-motors simultaneously $*9
L99MD01 application examples doc id 17242 rev 6 45/54 figure 16. driving 3 dc-motors simultaneously and 2 dc-motors sequentially figure 17. driving 7 dc-motors sequentially $*9 $*9
application examples L99MD01 46/54 doc id 17242 rev 6 figure 18. driving simultaneously 4 unipolar winded stepper motors in bipolar mode $*9
L99MD01 application examples doc id 17242 rev 6 47/54 figure 19. cost saving impact using L99MD01 as stepper motor driver inside hvac systems $*9
package and pcb thermal data L99MD01 48/54 doc id 17242 rev 6 8 package and pcb thermal data 8.1 powersso-36 thermal data figure 20. powersso-36 pc board $*9 note: board finish thickness 1.6 mm +/- 10%; board double layer and four layers; board dimension 129 mm x 60 mm; board material fr4; cu thickness 0.070 mm (outer layers); cu thickness 0.035mm (inner layers); thermal vias separation 1.2 mm; thermal via diameter 0.3 mm +/-0.08 mm; cu thickness on vias 0.025 mm; footprint dimension 4.1 mm x 6.5 mm
L99MD01 package and pcb thermal data doc id 17242 rev 6 49/54 figure 21. powersso-36 thermal impedance junction ambient =7+? &: 7lphv )rrwsulqw fp /d\hu $*9
package information L99MD01 50/54 doc id 17242 rev 6 9 package information 9.1 ecopack ? package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 9.2 powersso-36? mechanical data figure 22. powersso-36? package dimensions a g00066v1
L99MD01 package information doc id 17242 rev 6 51/54 l table 39. powersso-36 mechanical data symbol millimeters min. typ. max. a 2.15 - 2.45 a2 2.15 - 2.35 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 d (1) 1. ?d? and ?e? do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side (0.006?). 10.10 - 10.50 e 7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 g1 - - 0.06 h 10.1 - 10.5 h- -0.4 k0-8 l 0.55 - 0.85 m-4.3- n- -10 o-1.2- q-0.8- s-2.9- t-3.65- u-1- x 4.3 - 5.2 y 6.9 - 7.5
package information L99MD01 52/54 doc id 17242 rev 6 9.3 packing information figure 23. powersso-36 tube shipment (no suffix) figure 24. powersso-36 tape and reel shipment (suffix ?tr?) a c b gapgcft00002 all dimensions are in mm. base q.ty 49 bulk q.ty 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed gapgcft00003
L99MD01 revision history doc id 17242 rev 6 53/54 10 revision history table 40. document revision history date revision changes 22-mar-2010 1 initial release. 17-may-2010 2 updated features list. removed block diagram updated following tables: ? table 1: device summary ? table 3: pin description ? table 11: current monitor output updated section 2.3: standby mode , section 2.5: smps switched mode power supply and section 2.10: v s , v s2 , v sa , v sb monitoring . section 9.2: powersso-36? mechanical data : ? updated figure 22: powersso-36? package dimensions ? updated table 39: powersso-36 mechanical data 24-jan-2011 3 updated features list updated figure 2: power on reset table 8: supply : ?i vs : updated maximum value ?i vsx : updated test condition table 9: overvoltage and undervoltage detection : ?v suv off , v sauv off , v sbuv off : updated maximum value ?v suv hyst , v sauv hyst , v sbuv off , v sbuv hyst , v sov hyst , v s2ov hyst : updated minimum value table 10: switches : ?r onlslc 1-8 : updated maximum value ?i qlh , i qll : updated minimum, typical and maximum values ?i oldhs1-8 , i oldlshc1-8 , i oldlslc1-8 : updated test condition, minimum and maximum values table 11: current monitor output : ?i currhs1/2 acc : updated test condition and maximum value ?i currlshc1/2 acc , i currlslc1/2 acc : updated maximum value added table 12: current monitor dynamic characteristics table 13: smps switched mode power supply gate driver output : r smps : updated minimun and maximum values updated section 2.9: temperature warning and thermal shutdown added chapter 8: package and pcb thermal data 23-feb-2011 4 updated tables table 12: current monitor dynamic characteristics 19-sep-2013 5 updated disclaimer. 20-sep-2013 6 updated disclaimer and revision in all document.
L99MD01 54/54 doc id 17242 rev 6 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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